In contrast to static random-access memories (SRAMs) in which the stored information remains in the memory indefinitely, at least so long as these memories remain powered, dynamic memories have the particular feature of needing a periodic refresh of the stored information. This is so because of stray leakage currents which discharge the storage capacitor of each memory cell (memory point) of the memory plane. Among known memory cells of dynamic random-access memories, mention may be made of the one having two or three transistors, and those having a single transistor for which reading the information furthermore destroys this information. Mention may also be made of the four-transistor memory cells as described in French patent application No. 97 12818 assigned to the assignee of the present invention.
One of the major limitations of a dynamic memory is its power consumption in the inactive mode, that is, when no access is required of this memory either for reading or for writing. In a static memory in the inactive mode, the consumption is limited to the leakage currents of the CMOS circuits; however, in a dynamic memory it is necessary to refresh the memory, even if no read or write operation is requested. It is actually this refresh operation which will generate non-negligible power consumption incompatible with a low-consumption application.
A dynamic memory needs to be refreshed periodically. The refresh period is equal to the information retention time of the elementary memory point. In a dynamic random-access memory, this retention time is a parameter which is specified to correspond to the worst case. In other words, after numerous characterizations (tests, simulations, etc.) the minimum retention time is determined then the refresh of the random-access memory is specified with this minimum time. However, the retention time depends on a number of factors, such as the "process", the supply voltage and, above all, the temperature. The retention time can vary by a factor of 10,000.
The conventional so-called "worst-case" design approaches thus lead to dynamic random-access memories which have non-negligible consumption, in particular, in the inactive mode. The actual operating conditions would in fact lead to a much longer retention time than the one specified.